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Maxim > 方案 > 传输节点、接入节点、上/下路复用器和数字交叉连接

时钟恢复

数据资料
显示 标题/型号 关键优势
QV  PDF DS34T101、DS34T102、DS34T104、DS34T108、DS34S101、DS34S102、DS34S104和DS34S108评估板
DS34T108DK
QV  PDF 单/双/四/八通道TDM-Over-Packet芯片
DS34T101, DS34T102, DS34T104, DS34T108

支持包交换网络的CESoPSN、SAToP和TDMoIP传输，可支持8个E1/T1端口
QV  PDF Stratum 2/3E/3时钟卡IC
DS3101

符合SONET/SDH Stratum 3/3E标准的时钟卡IC
QV  PDF Stratum 3/3E/3时钟卡IC
DS3100

完备的单芯片SONET/SDH时钟卡方案
QV  PDF T1/E1/J1/64KCC BITS单元
DS26504
QV  PDF 四路T1/E1/J1收发器
DS21455, DS21458

业内首款4端口收发器，用于T1、E1、J1标准间的切换，无需外部元件
QV  PDF E1四收发器
DS21Q58
QV  PDF E1四收发器
DS21Q59
QV  PDF 3.3V、E1/T1/J1四线路接口
DS21448

3.3V E1/T1/J1、4端口线路接口单元，用于短程或长程通信系统
QV  PDF 高性能演示套件母板
DK2000
QV  PDF 低功耗、结构紧凑的2.5Gbps/2.7Gbps时钟恢复与数据再定时IC
MAX3873A
QV  PDF 四路、E1收发器
DS21Q50

四路、E1收发器，包含连接四路E1的全部功能
QV  PDF 622Mbps、3.3V时钟恢复与数据再定时IC，带有限幅放大器
MAX3676

高性能、低功耗622Mbps CDR



Key Specifications:   Clock and Data Recovery
Part Number Functions Target Operating Range (Gbps) Min. Data Rate (Mbps) Max. Data Rate (Mbps) Multirate Supply Voltage (V) Typ. Supply Current (mA) I/O Type Input Sens. (mV) Package Operating Temp. Range (°C)
MAX3873A 
•CDR
 1 to 4.5 2488 2670 Yes 3.3 79 CML 50 QFN/20
TQFN/20 		-40 to +85
MAX3676 
•CDR
 <1 622 622 No 3.3
5 		65 PECL  -  TQFP/32 -40 to +85
See All Clock and Data Recovery (8)

Key Specifications:   T/E Carrier & Packetized Design Kits
Part Number Overview Kit Product Line Kit Hardware Kit Software Technical Documentation
DS34T108DK  NEW! DS34T108DK EV-Kit TDM-over-Packet
•BNC Cables (2)
•BNC Converter (2)
•Cat- 5 Crossover Cable
•Cat- 5 Patch Cable
•Design Kit Chassis
•Power Cord
•Chipview Configuration Software
•Driver Source Code
•Example Application Source Code
•Data Sheet
•User's Guide
See All T/E Carrier & Packetized Design Kits (16)

Key Specifications:   T/E Carrier & Packetized Products
Part Number Transmission Standard Functions Number of Channels Input to Output Clocks (MHz) Supply Voltage (V) EV-Kit Package Smallest Available Package (max w/pins) (mm2)
DS26504  64kHz - G.703 II.2 Japanese 6312kHz Clock
64kHz - G.703 II.1 Japanese 64kHz Clock
64kHz Composite Clock - G.703 Level B
64kHz Composite Clock - G.703 Level A
64kHz Composite Clock - GR378
T1/E1/J1
•BITS Element
 1 0.008
0.064
1.544
2.048
6.312
19.44 		3.3 Yes LQFP/64 149
DS21455  T1/E1/J1
•Framer + LIU
 4  -  3.3  -  0/0  - 
DS21458  T1/E1/J1
•Framer + LIU
 4  -  3.3 Yes CSBGA/256 289
DK2000  ATM
E1
STS-1
T1/E1/J1
T1/J1
T3/E3 		 -   -   -  3.3
5 		 -  See Data Sheet  - 
DS21448  T1/E1/J1
•LIU
 4  -  3.3 Yes LQFP/128
TEPBGA/144 		289
DS21Q58  E1
•Framer + LIU
 4  -  3.3  -  LQFP/100 262
DS21Q59  E1
•Framer + LIU
 4  -  3.3 Yes LQFP/100 262
DS21Q50  E1
•Framer + LIU
 4  -  3.3  -  LQFP/100 262
See All T/E Carrier & Packetized Products (102)

Key Specifications:   TDM-Over-Packet
Part Number Number of Integrated T1/E1 LIU+Framer Number of T1/E1/Serial Streams Number of T3/E3, STS-1 Serial Ports Mapping Methods PSN Encapsulation Protocols 10/100 MAC Interface Processor Interface Package
DS34T101  NEW! 1 1 1 AAL1
CESoPSN
HDLC
SAToP
Structured
Structured with CSA
TDMoIP
Unstructured 		L2TPv3 (IPv4, IPv6)
MEF-8
MPLS
RTP
UDP (IPv4, IPv6) 		MII
RMII
SSMII 		16-Bit
32-Bit
SPI 		0/0
DS34T102  NEW! 2 2 1 AAL1
CESoPSN
HDLC
SAToP
Structured
Structured with CSA
TDMoIP
Unstructured 		L2TPv3 (IPv4, IPv6)
MEF-8
MPLS
RTP
UDP (IPv4, IPv6) 		MII
RMII
SSMII 		16-Bit
32-Bit
SPI 		0/0
DS34T104  NEW! 4 4 1 AAL1
CESoPSN
HDLC
SAToP
Structured
Structured with CSA
TDMoIP
Unstructured 		L2TPv3 (IPv4, IPv6)
MEF-8
MPLS
RTP
UDP (IPv4, IPv6) 		MII
RMII
SSMII 		16-Bit
32-Bit
SPI 		0/0
DS34T108  NEW! 8 8 1 AAL1
CESoPSN
HDLC
SAToP
Structured
Structured with CSA
TDMoIP
Unstructured 		L2TPv3 (IPv4, IPv6)
MEF-8
MPLS
RTP
UDP (IPv4, IPv6) 		MII
RMII
SSMII 		16-Bit
32-Bit
SPI 		0/0
See All TDM-Over-Packet (8)

Key Specifications:   Timing Card and Line Card ICs
Part Number Number of Independent DPLLs Number of Input Clocks Number of Differential Input Clocks Number of Output Clocks Number of Differential Output Clocks Input Clock Frequencies Output Clock Frequencies Number of DS1/E1/J1 Receivers Number of DS1/E1/J1 Transmitters Minimum DPLL Bandwidth (Hz) Maximum DPLL Bandwidth (Hz)
DS3100  2 14 2 11 3 2kHz and 4kHz
N x 19.44MHz
N x 8kHz up to 155.52MHz
N x DS1
N x E1 		2kHz
6.48MHz
8kHz
25.00MHz
51.84MHz
62.5MHz
125.00MHz
155.52MHz
311.04MHz
DS3
E3
N x 19.44MHz
N x DS1
N x DS2
N x E1 		2 2 0.0005 70
DS3101  2 14 2 11 3 2kHz and 4kHz
N x 19.44MHz
N x 8kHz up to 155.52MHz
N x DS1
N x E1 		2kHz
6.48MHz
8kHz
25.00MHz
51.84MHz
62.5MHz
125.00MHz
155.52MHz
311.04MHz
DS3
E3
N x 19.44MHz
N x DS1
N x DS2
N x E1 		0 0 0.0005 70
See All Timing Card and Line Card ICs (6)
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