基站/无线基础结构



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高速时钟与信号分配器

数据资料

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标题/型号

关键优势

QV PDF

MAX3673评估板
MAX3673EVKIT

QV PDF

低抖动频率合成器，可选择输入参考时钟
MAX3673

业内最佳的抖动指标，优于SerDes参考时钟规范

QV PDF

DS34T101、DS34T102、DS34T104、DS34T108、DS34S101、DS34S102、DS34S104和DS34S108评估板
DS34T108DK

QV PDF

MAX3674评估板
MAX3674EVKIT

QV PDF

MAX9390和MAX9391评估板
MAX9390EVKIT

QV PDF

高性能、双输出、网络时钟合成器
MAX3674

1.6ps周期间抖动和0.8%频率调谐

QV PDF

低抖动、精密时钟发生器，提供四路输出
MAX3624

0.36ps抖动和出色的电源噪声抑制

QV PDF

10MHz至51.84MHz TCXO
DS4026

数字TCXO在宽温范围内保持高精度

QV PDF

2:1复用器和1:2解复用器，带有环回
MAX9396

复用器/解复用器，450mV差分输出

通用的GPS接收器
MAX2769

利用通用的GNSS RF接收器改善GPS和GALILEO系统的性能并降低其成本

QV PDF

单/双/四/八通道TDM-Over-Packet芯片
DS34T101, DS34T102, DS34T104, DS34T108

支持包交换网络的CESoPSN、SAToP和TDMoIP传输，可支持8个E1/T1端口

QV PDF

Stratum 2/3E/3时钟卡IC
DS3101

符合SONET/SDH Stratum 3/3E标准的时钟卡IC

QV PDF

Stratum 3/3E/3时钟卡IC
DS3100

完备的单芯片SONET/SDH时钟卡方案

QV PDF

集成了VCXO的高精度时钟发生器
MAX9450, MAX9451, MAX9452

首款SONET时钟发生器, 集成了VCXO和延时电路, 可替代昂贵的VCXO及其外部失效保护电路

QV PDF

3.3V、单芯片、1Mb非易失SRAM
DS2045L

QV PDF

3.3V、单芯片、8Mb非易失SRAM，带有时钟
DS3065W

QV PDF

3.3V、单芯片、4Mb非易失SRAM，带有时钟
DS3050W

QV PDF

多输出时钟发生器，带有扩频功能
MAX9492

扩频合成器能够为网络路由或交换机的时钟分配提供多路时钟

QV PDF

3.3V、单芯片、8Mb非易失SRAM
DS2065W

QV PDF

3.3V、单芯片、4Mb非易失SRAM
DS2050W

QV PDF

T1/E1/J1/64KCC BITS单元
DS26504

QV PDF

单芯片、256k位非易失SRAM
DS2030AB, DS2030Y

QV PDF

MAX3982评估板
MAX3982EVKIT

QV PDF

多输出网络时钟发生器
MAX9489

提供多时钟输出的时钟发生器，用于网络路由器

QV PDF

SFP铜缆预加重驱动器
MAX3982

QV PDF

8kHz参考时钟合成器，提供35.328MHz倍频输出
MAX9486

可理想用于xDSL CO线卡和电信系统的时钟发生器，具有低抖动时钟输出

QV PDF

八路T1/E1/J1收发器
DS26528

QV PDF

四路T1/E1/J1收发器
DS26524

低功耗、低成本SCT，引脚及软件兼容于八通道DS26528，可方便地移植到多端口设备，提供无铅封装

QV PDF

任意逻辑至LVDS、双路、2 x 2交叉点开关
MAX9390, MAX9391

双路、任意逻辑至LVDS、2 x 2交叉点开关，确保工作在1.50GHz最大工作频率

QV PDF

LVDS或LVTTL/LVCMOS输入至14路LVTTL/LVCMOS输出的时钟驱动器
MAX9160

QV PDF

400Mbps、低抖动、低噪声LVDS转发器，SC70封装
MAX9180

QV PDF

ECL/PECL相频检测器
MAX9382, MAX9383

QV PDF

低抖动、800Mbps、10端口、LVDS转发器，100Ω驱动
MAX9153, MAX9154

QV PDF

四路、总线式LVDS驱动器，引脚按信号流向排列
MAX9129

QV PDF

10位总线LVDS解串器
MAX9206, MAX9208

QV PDF

10位、总线式LVDS串行器
MAX9205, MAX9207

QV PDF

800Mbps、LVDS/LVPECL至LVDS、2 x 2交叉点开关
MAX9152

QV PDF

低抖动、10端口LVDS转发器
MAX9150

业内抖动最低的多端口LVDS中继器

Key Specifications: Clock Generators

Part Number

Applications

f_IN (min) (MHz)

f_IN (max) (MHz)

f_OUT (min) (MHz)

f_OUT (max) (MHz)

Fixed or Continuous Frequency

Output Levels

Number of Outputs

Number of PLLs

Programmability

Spread Spectrum

Output Jitter (ps RMS)

Supply Voltage (V)

Package

MAX3673 NEW!

•	3G Wireless Base Stations

•	Clock Distribution

•	Frequency Translation

•	Jitter Cleanup

61.44

307.2

61.44

307.2

Fixed

LVPECL

0.3

3.3

TQFN/56

MAX3674

•	General Purpose

21.25

1360

Continuous

LVPECL

I²C
Pin

0.9

3.3

TQFP/48

MAX3624

•

Ethernet

•	Fibre Channel

•	InfiniBand

•

PCIe

•

SONET/SDH

40.5

62.5

312.5

Fixed

LVCMOS
LVPECL

0.14

3.3

TQFN/32

MAX9451

•

Ethernet

•	Fibre Channel

•

GSM

•

SONET/SDH

•

UMTS

•

W-CDMA

0.008

500

160

Continuous

HSTL

I²C

0.8

2.5
3.3

TQFP-EP/32

MAX9450

•

Ethernet

•	Fibre Channel

•

GSM

•

SONET/SDH

•

UMTS

•

W-CDMA

0.008

500

160

Continuous

LVPECL

I²C

0.8

2.5
3.3

TQFP-EP/32

MAX9452

•

Ethernet

•	Fibre Channel

•

GSM

•

SONET/SDH

•

UMTS

•

W-CDMA

0.008

500

160

Continuous

LVDS

I²C

0.8

2.5
3.3

TQFP-EP/32

MAX9492

•

Ethernet

•	General Purpose

133.3

Fixed

LVCMOS

I²C

Yes

3.3

TQFN/20

MAX9489

•

Ethernet

•	General Purpose

133.3

Fixed

LVCMOS

I²C

3.3

TQFN/32

MAX9486

•

T1/E1

•

T3/E3

•

xDSL

0.008

35.328

Fixed

LVCMOS

3.3

TSSOP/24

See All Clock Generators (28)

Key Specifications: Equalizers (Cable and Circuit Board)

Part Number

Min. Data Rate (Mbps)

Max. Data Rate (Mbps)

Max. Reach @ Max. Data Rate

Supply Voltage (V)

I/O Type

Channels Per Part

Typ. Rx Eq. @ Max. Rate (dB)

Typ. Tx Eq. @ Max. Rate (dB)

Package

Smallest Available Package (max w/pins) (mm²)

Operating Temp. Range (°C)

MAX3982

1000

4250

1m FR4
15m Cable

3.3

CML

TQFN/16

0 to +85

See All Equalizers (Cable and Circuit Board) (19)

Key Specifications: GPS Receivers

Part Number

Ref. Clock Freq (MHz)

IF Output Freq. (MHz)

IF Output Bit(s) CMOS

Noise Fig. (typ) (dB)

Supply Voltage (V)

Supply Current (mA)

Applications

Solutions

Band/Freq (MHz)

Features

Footprint (mm x mm)

Package

Smallest Available Package (max w/pins) (mm²)

Industry Qualified

MAX2769

8 to 44

2.5

1 to 3

1.4

2.7 to 3.3

•

GLONASS

•

GPS

•

Gailileo

Cellular Handsets
Personal Navigation Devices
Smart Phones

1550 to 1610

•	1.4dB Cascaded Noise Figure

•	Dual-Input LNA Supports Active and Passive Antenna

•	Low-IF, Zero-IF, Software DSP Interfaces

5.0 x 5.0

TQFN/28

Automotive - General

See All GPS Receivers (3)

Key Specifications: High-Speed Interconnect (Differential Signaling)

Part Number

Features

Rx Signal Type

Tx Signal Type

Functions

Number of Rx

Number of Tx

Data Rates (Mbps)

Propagation Delay (max) (ps)

Supply Voltage (V)

MAX9450

LVPECL

2.5
3.3

MAX9390

•	Anything Inputs

•	Cross-Flow Pinout

•	High-Level Input Fail-Safe Detection

CML
HSTL
LVDS
LVPECL

LVDS

•

Switch

565

3.3

MAX9391

•	Anything Inputs

•	Cross-Flow Pinout

•	Low-Level Input Fail-Safe Detection

CML
HSTL
LVDS
LVPECL

LVDS

•

Switch

565

3.3

MAX9160

•	Fail-Safe Inputs

•	High-ESD Rating

•	Integrated Output Termination

•	Rx Hi-Z at Power-Off

•	Tx Hi-Z Enable Pins

CMOS
LVDS
LVTTL

CMOS
LVTTL

•	Fan-Out Buffer

9000

3.3

MAX9180

•	Fail-Safe Inputs

•	Rx/Tx Hi-Z at Power-Off

LVDS

•

Buffer

400

2800

3.3

MAX9153

•	Fail-Safe Inputs

•	Tx Hi-Z at Power-Off

LVDS

•	Fan-Out Buffer

800

3300

3.3

MAX9154

•	Tx Hi-Z at Power-Off

LVPECL

LVDS

•	Fan-Out Buffer

800

3300

3.3

MAX9382

•	Guaranteed Min. Output Short-Pulse Duration

ECL
PECL

•	Phase Frequency Detector

1360

MAX9383

•	Guaranteed Min. Output Short-Pulse Duration

ECL
PECL

•	Phase Frequency Detector

1360

MAX9129

•	Flow-Through Pinout

•	Tx Hi-Z Enable Pins

•	Tx Hi-Z at Power-Off

CMOS
LVTTL

LVDS

•	Level Translator

200

3000

3.3

MAX9206

•	Auto Clock Recovery

•	Fail-Safe Inputs

•	Fast Pseudo Random Lock

•	Standalone Deserializer

LVDS

CMOS
LVTTL

•	Deserializer

400

3.3

MAX9208

•	Auto Clock Recovery

•	Fail-Safe Inputs

•	Fast Pseudo Random Lock

•	Standalone Deserializer

LVDS

CMOS
LVTTL

•	Deserializer

600

3.3

MAX9152

•	Pin-Programmable Configuration

•	Pin-Programmable Output Resistance

LVDS
LVPECL

LVDS

•

Switch

800

3400

3.3

MAX9205

•	Programmable Active Edge on Input Latch

•	Standalone Serializer

CMOS
LVTTL

LVDS

•	Serializer

400

3.3

MAX9207

•	Programmable Active Edge on Input Latch

•	Standalone Serializer

CMOS
LVTTL

LVDS

•	Serializer

660

3.3

MAX9150

•	Fail-Safe Inputs

•	Low Power Shutdown Mode

•	Rx Hi-Z at Power-Off

LVDS

•	Fan-Out Buffer

400

3500

3.3

See All High-Speed Interconnect (Differential Signaling) (132)

Key Specifications: Oscillator Modules

Part Number

Frequency

Oscillator Type

Tuning Adjustment Type

Frequency Output Type

Freq. Stability vs. Temp. @-40 to +85°C (±ppm)

Frequency Stability vs. Supply Voltage (±ppm/V)

Frequency Stability vs. Aging (±ppm)

Supply Voltage (V)

DS4026

12.8MHz
19.44MHz
20MHz
38.88MHz
40MHz
51.84MHz

TCXO

Digital

CMOS Push-Pull

±2 (max)

2 (2-15 Years)

3.3 ±5%

See All Oscillator Modules (28)

Key Specifications: T/E Carrier & Packetized Design Kits

Part Number

Overview

Kit Product Line

Kit Hardware

Kit Software

Technical Documentation

DS34T108DK NEW!

TDM-over-Packet

•	BNC Cables (2)

•	BNC Converter (2)

•	Cat- 5 Crossover Cable

•	Cat- 5 Patch Cable

•	Design Kit Chassis

•	Power Cord

•	Chipview Configuration Software

•	Driver Source Code

•	Example Application Source Code

•	Data Sheet

•	User's Guide

See All T/E Carrier & Packetized Design Kits (16)

Key Specifications: T/E Carrier & Packetized Products

Part Number

Transmission Standard

Functions

Number of Channels

Input to Output Clocks (MHz)

Supply Voltage (V)

EV-Kit

Package

Smallest Available Package (max w/pins) (mm²)

DS26524

T1/E1/J1

•	Framer + LIU

External Master Clock can be a multiple of 1.544 or 2.048

3.3

Yes

0/0

DS26528

T1/E1/J1

•	Framer + LIU

External Master Clock can be a multiple of 1.544 or 2.048

3.3

Yes

0/0

DS26504

64kHz - G.703 II.2 Japanese 6312kHz Clock
64kHz - G.703 II.1 Japanese 64kHz Clock
64kHz Composite Clock - G.703 Level B
64kHz Composite Clock - G.703 Level A
64kHz Composite Clock - GR378
T1/E1/J1

•	BITS Element

0.008
0.064
1.544
2.048
6.312
19.44

3.3

Yes

LQFP/64

149

See All T/E Carrier & Packetized Products (102)

Key Specifications: TDM-Over-Packet
Part Number	Number of Integrated T1/E1 LIU+Framer	Number of T1/E1/Serial Streams	Number of T3/E3, STS-1 Serial Ports	Mapping Methods	PSN Encapsulation Protocols	10/100 MAC Interface	Processor Interface	Package
DS34T101 NEW!	1	1	1	AAL1 CESoPSN HDLC SAToP Structured Structured with CSA TDMoIP Unstructured	L2TPv3 (IPv4, IPv6) MEF-8 MPLS RTP UDP (IPv4, IPv6)	MII RMII SSMII	16-Bit 32-Bit SPI	0/0
DS34T102 NEW!	2	2	1	AAL1 CESoPSN HDLC SAToP Structured Structured with CSA TDMoIP Unstructured	L2TPv3 (IPv4, IPv6) MEF-8 MPLS RTP UDP (IPv4, IPv6)	MII RMII SSMII	16-Bit 32-Bit SPI	0/0
DS34T104 NEW!	4	4	1	AAL1 CESoPSN HDLC SAToP Structured Structured with CSA TDMoIP Unstructured	L2TPv3 (IPv4, IPv6) MEF-8 MPLS RTP UDP (IPv4, IPv6)	MII RMII SSMII	16-Bit 32-Bit SPI	0/0
DS34T108 NEW!	8	8	1	AAL1 CESoPSN HDLC SAToP Structured Structured with CSA TDMoIP Unstructured	L2TPv3 (IPv4, IPv6) MEF-8 MPLS RTP UDP (IPv4, IPv6)	MII RMII SSMII	16-Bit 32-Bit SPI	0/0
See All TDM-Over-Packet (8)

Key Specifications: Timekeeping & Real-Time Clocks

Part Number

Functions

Date/ Time Format (hh = sec/100)

Interface

Supply Voltage (V)

Memory Type

Memory Size (Bytes)

Number of Time of Day Alarms

DS3050W

•	Watchdog Timekeeper

YYYY-MM-DD/ HH:MM:SS

Bytewide

3.3

NV SRAM

512K

DS3065W

•	Watchdog Timekeeper

YYYY-MM-DD/ HH:MM:SS

Bytewide

3.3

NV SRAM

See All Timekeeping & Real-Time Clocks (85)

Key Specifications: Timing Card and Line Card ICs
Part Number	Number of Independent DPLLs	Number of Input Clocks	Number of Differential Input Clocks	Number of Output Clocks	Number of Differential Output Clocks	Input Clock Frequencies	Output Clock Frequencies	Number of DS1/E1/J1 Receivers	Number of DS1/E1/J1 Transmitters	Minimum DPLL Bandwidth (Hz)	Maximum DPLL Bandwidth (Hz)
DS3100	2	14	2	11	3	2kHz and 4kHz N x 19.44MHz N x 8kHz up to 155.52MHz N x DS1 N x E1	2kHz 6.48MHz 8kHz 25.00MHz 51.84MHz 62.5MHz 125.00MHz 155.52MHz 311.04MHz DS3 E3 N x 19.44MHz N x DS1 N x DS2 N x E1	2	2	0.0005	70
DS3101	2	14	2	11	3	2kHz and 4kHz N x 19.44MHz N x 8kHz up to 155.52MHz N x DS1 N x E1	2kHz 6.48MHz 8kHz 25.00MHz 51.84MHz 62.5MHz 125.00MHz 155.52MHz 311.04MHz DS3 E3 N x 19.44MHz N x DS1 N x DS2 N x E1	0	0	0.0005	70
See All Timing Card and Line Card ICs (6)