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Maxim > 方案 > 高级主板方案:ATCA/MicroTCA

时钟同步

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QV  PDF Stratum 3/3E时钟卡IC
DS3100

完备的单芯片SONET/SDH时钟卡方案



Key Specifications:   Timing Card and Line Card ICs
Part Number Number of Independent DPLLs Number of Input Clocks Number of Differential Input Clocks Number of Output Clocks Number of Differential Output Clocks Input Clock Frequencies Output Clock Frequencies Number of DS1/E1/J1 Receivers Number of DS1/E1/J1 Transmitters Minimum DPLL Bandwidth (Hz) Maximum DPLL Bandwidth (Hz)
DS3100  2 14 2 11 3 2kHz and 4kHz
N x 19.44MHz
N x 8kHz up to 155.52 MHz
N x DS1
N x E1
155.52MHz
2kHz
311.04MHz
51.84MHz
6.48MHz
62.5MHz
8kHz
DS3
E3
N x 19.44MHz
N x DS1
N x DS2
N x E1
2 2 0.0005 70
See All Timing Card and Line Card ICs (1)



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