The MAX19516 dual-channel, analog-to-digital converter (ADC) provides 10-bit resolution and a maximum sample rate of 100Msps.
The MAX19516 analog input accepts a wide 0.4V to 1.4V input common-mode voltage range, allowing DC-coupled inputs for a wide range of RF, IF, and baseband front-end components. The MAX19516 provides excellent dynamic performance from baseband to high input frequencies beyond 400MHz, making the device ideal for zero-intermediate frequency (ZIF) and high-intermediate frequency (IF) sampling applications. The typical signal-to-noise ratio (SNR) performance is 60dBFS and typical spurious-free dynamic range (SFDR) is 82dBc at fIN = 70MHz and fCLK = 100MHz.
The MAX19516 operates from a 1.8V supply. Additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5V to 3.3V supply (AVDD). The digital output drivers operate on an independent supply voltage (OVDD) over the 1.8V to 3.5V range. The analog power consumption is only 57mW per channel at VADD = 1.8V. In addition to low operating power, the MAX19516 consumes only 1mW in powerdown mode and 17mW in standby mode.
Various adjustments and feature selections are available through programmable registers that are accessed through the 3-wire serial-port interface. Alternatively, the serial-port interface can be disabled, with the three pins available to select output mode, data format, and clock-divider mode. Data outputs are available through a dual parallel CMOS-compatible output data bus that can also be configured as a single multiplexed parallel CMOS bus.
The MAX19516 is available in a small 7mm x 7mm 48-pin thin QFN package and is specified over the -40°C to +85°C extended temperature range.
Refer to the MAX19505, MAX19506, and MAX19507 data sheets for pin- and feature-compatible 8-bit, 65Msps, 100Msps, and 130Msps versions, respectively. Refer to the MAX19515 and MAX19517 data sheets for pin- and feature-compatible 10-bit, 65Msps and 130Msps versions, respectively.
关键特性
应用/使用
Very-Low-Power Operation (57mW/Channel at 100Msps)
1.8V or 2.5V to 3.3V Analog Supply
Excellent Dynamic Performance
60dBFS SNR at 70MHz
82dBc SFDR at 70MHz
User-Programmable Adjustments and Feature Selection through an SPI™ Interface
Selectable Data Bus (Dual CMOS or Single Multiplexed CMOS)
DCLK Output and Programmable Data Output Timing Simplifies High-Speed Digital Interface
Very Wide Input Common-Mode Voltage Range (0.4V to 1.4V)
Very High Analog Input Bandwidth (> 850MHz)
Single-Ended or Differential Analog Inputs
Single-Ended or Differential Clock Input
Divide-by-One (DIV1), Divide-by-Two (DIV2), and Divide-by-Four (DIV4) Clock Modes
Two's Complement, Gray Code, and Offset Binary Output Data Format
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