Abstract: The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses an external high-Q voltage-controlled oscillator (VCO) to create a very low jitter clock signal phase-locked to a system clock input. It is ideal for SONET OC-48 or OC-192 applications requiring a very low jitter 156 MHZ or 622MHz clock signal. When used with a low-jitter voltage-controlled SAW oscillator (VCSO) or a voltage-controlled crystal oscillator (VCX), the total system jitter can be less than 1 psrms. This design note provides analysis and examples that address optimal PLL configuration, including external component values, internal divider settings, and internal phase detector gain for low-jitter applications. 你所查询的应用笔记提供Acrobat PDF格式： APPLICATION NOTE 1032:MAX3670: Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator (PDF, 57kB) 免费Acrobat PDF阅读软件可从以下网站获得： http://chinese-s.adobe.com/products/acrobat/readstep2.html 我们期待您的反馈！ 喜欢？不喜欢？有待改善？或为我们提供建议？请与我们联系 — 我们将根据您的意见或建议改善我们的工作。 网页评价或提供建议 自动更新 需要自动接收最新发布的应用笔记吗？请订阅EE-Mail™ (English only)。 更多信息   APP 1032: Jun 08, 2001 MAX3670 低抖动、155MHz/622MHz时钟发生器 完整的数据资料 (PDF, 852kB) 免费样品   下载，PDF格式 (57kB)  AN1032, AN 1032, APP1032, Appnote1032, Appnote 1032