Transmit PLL Output. 1544kHz, 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL
17
TCLK
I
Transmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz primary clock. By using TCSS0 and TCSS1 pins, may be selected by the TX PLL mux to provide a clock to the transmit section
6331
TCSS0 TCSS1
I
Transmit Clock Source Select 0 and 1 Selects the output of the TX PLL Clock Mux function.
TCSS1
TCSS0
Transmit Clock (TX Clock) Source
0
0
The TCLK pin is the source of transmit clock
0
1
The PLL_CLK is the source of transmit clock
1
0
The scaled signal at MCLK as the transmit clock
1
1
The signal present at RCLK is the transmit clock
发送侧
Pin
Name
Type
Function
21
TSER
I
Transmit Serial Data. Source of transmit data sampled on the falling edge of the selected transmit clock. In normal operation the selected transmit clock is output at the TCLKO pin.
23
TS_8K_4
I
TSYNC, 8kHz Sync, 400Hz Sync (400Hz Sync N/A in HW mode.)T1/E1 Mode: A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. 64KCC Mode: Establishes the boundary for the 8kHz portion of the composite clock.
18
TCLKO
O
Transmit Clock Output. In normal operation this output is the selected transmit clock from the TX_PLL, TCLK pin, or the recovered clock (RCLK). When remote loopback is enabled this pin will output the recovered network clock.
20
TPOSO
O
Transmit Positive-Data Output. In T1 or E1 mode, updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. In 64KCC or 6312 mode, this pin will be low.
19
TNEGO
O
Transmit Negative-Data Output. In T1 or E1 mode, updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. In 64KCC or 6312 mode, this pin will be low.
Receive Sync/ 8kHZ Clock. T1/E1 Mode: An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (RSM pin = 0) or multiframe (RSM pin = 1) boundaries. 64KCC Mode: This pin will output the extracted 8kHz portion of the composite clock signal. 6312K Mode: This pin will be in a high-impedance state.
27
400HZ
O
400HZ Clock OutputT1/E1 Mode: This pin will be in a high-impedance state.64KCC Mode: This pin will output the 400Hz clock if enabled.6312K Mode: This pin will be in a high-impedance state.
28
RSER
O
Receive Serial DataT1/E1 Mode: This is the received NRZ serial data updated on rising edges of RCLK. 64KCC Mode: This pin will be in a high-impedance state.6312K Mode: This pin will be in a high-impedance state.
30
RLOF_CCE
O
Receive Loss of Frame or Composite Clock Error T1/E1 Mode: Set when the receive synchronizer is searching for frame alignment (RLOF mode). 64KCC Mode: Active high when errors are detected in the 8kHz clock or 400Hz clock6312K Mode: This pin will be in a high-impedance state.
32
RLOS
O
Receive Loss of SignalT1 Mode: High when 192 consecutive zeros detected.E1 Mode: High when 255 consecutive zeros detected.64KCC Mode: High when consecutive zeros detected for 130ms typically.6312K Mode: High when consecutive zeros detected for 65ms typically.
29
RAIS
O
Receive Alarm Indication SignalT1 Mode: Will toggle high when receive Blue Alarm is detected.E1 Mode: Will toggle high when receive AIS is detected.64KCC Mode: This pin will be in a high-impedance state.6312K Mode: This pin will be in a high-impedance state.
控制器接口
Pin
Name
Type
Function
46
JACKS
I
JA Clock Source SelectJA Clock Select. Set this pin high for T1 mode operation when either a 2.048MHz, 4.096MHz, 8.192MHz or 16.382MHz signal is applied at MCLK.
14 49 48 62
TMODE0 TMODE1 TMODE2 TMODE3
I
Transmit Mode Select 0, 1, 2, 3. Used to configure the transmit-operating mode. See Transmit Path Operating Mode below:
Tri-State Control and Device Reset. TSTRST high tri-states all output and I/O pins. Set low for normal operation. Useful for in-board level testing.
57 59
BIS0 BIS1
I
Bus Interface Mode Select 1, 0. These bits select the controller interface mode of operation. BIS0 = 1 and BIS1 = 1 selects Hardware Mode
6
RITD
I
Receive Internal Termination DisableThe internal receive termination value is dependent on the state of the RMODEx pins. 0 = Enable the internal receive termination. 1 = Disable the internal receive termination.
5
TITD
I
Transmit Internal Termination DisableThe internal transmit termination value is dependent on the state of the TMODEx pins. 0 = Enable the internal transmit termination. 1 = Disable the internal transmit termination.
34 61 64
RMODE0 RMODE1 RMODE2 RMODE3
I
Receive Mode Select 0, 1, 2, 3. Used to configure the receiver-operating mode. See Receive Path Operating Mode below:
接收通道工作模式
Rmode3 Pin 64
Rmode2 Pin 61
Rmode1 Pin 4
Rmode0 Pin 3
Receive Path Operating Mode
0
0
0
0
T1 D4
0
0
0
1
T1 ESF
0
0
1
0
J1 D4
0
0
1
1
J1 ESF
0
1
0
0
E1 FAS
0
1
0
1
E1 CAS
0
1
1
0
E1 CRC4
0
1
1
1
E1 CAS and CRC4
1
0
0
0
E1 G.703 2048kHz Synchronization Interface
1
0
0
1
64kHz + 8kHz Synchronization Interface
1
0
1
0
64kHz + 8kHz + 400Hz Synchronization Interface
1
0
1
1
6312kHz Synchronization Interface
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
Pin
Name
Type
Function
2
TSM
I
TS_8K_4 Mode Select In T1 or E1 operation, selects frame or multiframe mode for the TS_8K_4 pin. 0 = Frame Mode. 1 = Multiframe Mode.
1
RSM
I
RS_8K Mode Select Selects frame or multiframe pulse at RS_8K pin. 0 = Frame Mode. 1 = Multiframe Mode.
15 16
MPS0 MPS1
I
MCLK Prescaler Select 0 and 1 Sets the prescale value for the PLL. T1 Mode
MCLK (MHz)
MPS1
MPS0
JACKS
1.544
0
0
0
3.088
0
1
0
6.176
1
0
0
12.352
1
1
0
2.048
0
0
1
4.096
0
1
1
8.192
1
0
1
16.384
1
1
1
E1 Mode
MCLK (MHz)
MPS1
MPS0
JACKS
2.048
0
0
0
4.096
0
1
0
8.192
1
0
0
16.384
1
1
0
10
TAIS
I
Transmit AIS In T1/E1 operating modes, the transmitter will transmit an AIS pattern when high. This pin is ignored in all other operating modes. 0 = Normal Transmission. 1 = Transmit AIS Alarm.
9
E1TS
I
E1 Termination Select Selects the E1 internal termination value at both the transmitter and receiver. This pin is ignored in all other operating modes. 0 = 120Ω termination 1 = 75Ω termination
55
HBE
I
Transmit and Receive B8ZS/HDB3 Enable Enables transmit and receive B8ZS/HDB3 when in T1/E1 operating modes. 0 = HDB3/B8ZS disabled 1 = HDB3/B8ZS enabled
60
RLB
I
Remote Loopback Enable In this loopback, data received at RTIP and RRING will be looped back to the transmit LIU. Received data will continue to pass through the receive-side framer of the DS26502 as it would normally, and the data from the transmit side formatter will be ignored. This function is only valid when the transmit side and receive side are in the same operating mode. 0 = Remote Loopback disabled 1 = Remote Loopback enabled
11 12 13
L0 L1 L2
I
Line Build-Out Select 0, 1, 2. Selects the line build-out value.For E1 see E1 Line Build-Out below: For T1 see T1 Line Build Out below:
E1线路补偿
L2 PIN 13
L1 PIN 12
L0 PIN 11
Application
N (1)
Return Loss
Rt (1)
0
0
0
75Ω normal
1:2
N.M. (2)
0
0
0
1
120Ω normal
1:2
N.M. (2)
0
1
0
0
75Ω with high return loss (1)
1:2
21dB
6.2Ω
1
0
1
120Ω with high return loss (1)
1:2
21dB
11.6Ω
1
1
0
Reserved
—
—
—
1
1
1
Reserved
—
—
—
T1线路补偿
L2 PIN 13
L1 PIN 12
L0 PIN 11
Application
N (1)
Return Loss
Rt (1)
0
0
0
DSX-1 (0 to 133 feet)/0dB CSU
1:2
N.M.
0
0
0
1
DSX-1 (133 to 266 feet)
1:2
N.M.
0
0
1
0
DSX-1 (266 to 399 feet)
1:2
N.M.
0
0
1
1
DSX-1 (399 to 533 feet)
1:2
N.M.
0
1
0
0
DSX-1 (533 to 655 feet)
1:2
N.M.
0
1
0
1
Reserved
—
—
—
1
1
0
Reserved
—
—
—
1
1
1
Reserved
—
—
—
注1：该模式下TTD引脚必须接高电平。
注2：N.M. = 无意义
JTAG
Pin
Name
Type
Function
34
JTCLK
I
JTAG Clock. This clock input is typically a low-frequency (less than 10MHz), 50% duty-cycle clock signal.
33
JTMS
I
JTAG Mode Select (with Pullup). This input signal is used to control the JTAG controller state machine and is sampled on the rising edge of JTCLK.
36
JTDI
I
JTAG Data Input (with Pullup). This input signal is used to input data into the register that is enabled by the JTAG controller state machine and is sampled on the rising edge of JTCLK.
37
JTDO
O
JTAG Data Output. This output signal is the output of an internal scan-shift register enabled by the JTAG controller state machine, and is updated on the falling edge of JTCLK. The pin is in the high-impedance mode when a register is not selected or when the JTRST signal is high. The pin goes into and exits the high impedance mode after the falling edge of JTCLK
35
JTRST
I
JTAG Reset (Active Low). This input forces the JTAG controller logic into the reset state and forces the JTDO pin into high impedance when low. This pin should be low while power is applied and set high after the power is stable. The pin can be driven high or low for normal operation, but must be high for JTAG operation.
线路接口
Pin
Name
Type
Function
44
MCLK
I
Master Clock Input. A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS26502 in T1-only operation, a 1.544MHz (50ppm) clock source can be used.
41
RTIP
I
Receive Tip. Analog input for clock recovery circuitry. This pin connects through a 1:1 transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.
42
RRING
I
Receive Ring. Analog input for clock recovery circuitry. This pin connects through a 1:1 transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.
51
TTIP
O
Transmit Tip. Analog line-driver output. This pin connects through a 1:2 step-up transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.
54
TRING
O
Transmit Ring. Analog line-driver output. This pin connects through a 1:2 step-up transformer to the network. See the Line Interface Unit section of the DS26502 data sheet for details.
50
THZE
I
Transmit High-Impedance Enable. When high, TTIP and TRING will be placed into a high-impedance state.
电源
Pin
Name
Type
Function
7,24,58
DVDD
—
Digital Positive Supply. 3.3V, ±5%. Should be tied to the RVDD and TVDD pins.
38
RVDD
—
Receive Analog Positive Supply. 3.3V, ±5%. Should be tied to the DVDD and TVDD pins.
53
TVDD
—
Transmit Analog Positive Supply. 3.3V, ±5%. Should be tied to the DVDD and RVDD pins.
8,22,56
DVSS
—
Digital Signal Ground. 0.0V. Should be tied to the RVSS and TVSS pins.
40,43,45
RVSS
—
Receive Analog Signal Ground. 0.0V. Should be tied to the DVSS and TVSS pins.
52
TVSS
—
Transmit Analog Signal Ground. 0.0V. Should be tied to the DVSS and RVSS pins.
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